1. Field of the Invention
The present invention relates generally to a unique cell structure for use in flash memory and, more particularly, to a vertically integrated flash memory cell which implements a pair of floating gates fabricated as sidewall spacers within a trench and to a method for fabricating the memory cell.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic memory comes in a variety of forms and may be used for a variety of applications. One type of commonly used memory is flash memory. Flash memory is a solid state storage device which provides easy and fast information storage. Flash memory is a type of electrically erasable programmable read-only memory (EEPROM) that can be erased and programmed through exposure to an electrical charge. Flash memory allows data to be written or erased in blocks rather than one byte at a time as with typical EEPROM devices, thereby making flash memory considerably faster.
Flash memory generally includes a grid of columns and rows forming an array of flash memory cells. Each cell generally comprises two transistors separated by a thin oxide layer. One of the transistors serves as the floating gate while the other serves as the control gate. The floating gate is coupled to the row or wordline through the control gate. Single data bits or multiple data bits can be stored in the memory cells by placing various levels of charge on the floating gate of the cell transistor. By storing differing levels of charge and thus obtaining different levels of threshold voltage Vt, a cell can store more than one bit of information therein. For example, to facilitate the storage of two binary bits, four levels of charge and corresponding levels of Vt may be used. During a read operation, a decoder senses the transition threshold Vt to determine the corresponding binary value of the multi-bit information (e.g. 00, 01, 10, 11). Disadvantageously, storing higher densities of binary bits in each cell to increase the number of voltage levels Vt used to store the higher bit densities introduces problems in the memory array including a higher operating voltage, more power dissipation, and increased circuit complexity for reading, erasing, and decoding the binary information. Further, if the number of charge levels increases without increasing the supply voltage, it becomes increasingly difficult to detect and distinguish the correct stored charge levels.
One technique for alleviating some of the problems associated with the storage of the multi-bit binary information in a memory cell is to provide two separate floating gates for each transistor within the memory cell. The control gate of the transistor is connected to a wordline provided over both floating gates while each of the source and drain regions of the transistor are connected to respective digit lines. Dual floating gate transistors distribute or partition the total charge in the transistor over each of the two floating gates, rather than a single floating gate. One advantage of dual floating gate transistors is that the dual floating gates allow for better control of the total charge in the transistor, as can be appreciated by those skilled in the art.
The processing of such structures is often costly and complex, especially with ever-increasing demands for smaller structures. Providing multi-bit flash cells and single bit flash cells incorporating dual floating gate patterns with less cumbersome and less costly processing techniques would be advantageous.